A common model for network processing consists of a multi-level approach. This is common in many Ethernet LAN protocols such as IEEE 802.3. The model typically includes 3 major levels, namely a) Top: Logical-Link control; b) Middle: Medium Access Control (MAC); and c) Bottom: Physical interface (PHY).
A wireless LAN configuration compliant to IEEE 802.11 is similar to its wired counterpart and has the same three levels. Traditionally, the top Logical-Link control tasks are handled by software running on a HOST processor. The middle level is the responsibility of a MAC processor, which handles all frame traffic between the HOST and the PHY level.
In a typical wireless local area network (WLAN) configuration, a portable or mobile device (e.g., a laptop personal computer) normally includes a HOST processor and a PCI card or PCMCIA card. On this card resides a Medium Access Control (MAC) processing system, a PHY (physical layer) processing device (e.g., a digital signal processor), and a main memory. The MAC processing system includes a MAC processor (e.g., an embedded processor), which is a multi-functional processor engine responsible for a variety of different processing tasks associated with the wireless communications. The PHY processing device performs such functions as encoding/decoding waveforms.
With wireless local area networks (LANs), high data rates (e.g., 56 MB/s or greater) are now attainable using new technologies such as Orthogonal Frequency Division Multiplexing (OFDM), as specified in the latest IEEE wireless standard 802.11b.
The present invention overcomes the slow data transfer rates of prior art data transfer systems to provide a data transfer system that provides the necessary throughput required by the higher data processing rates.